1. Field of the Invention
The present invention relates to a corner clamp and, more particularly, to a 5V tolerant corner clamp with a keep off circuit.
2. Description of the Related Art
An electrostatic discharge (ESD) protection circuit is a circuit that protects the input/output transistors of a semiconductor chip from an ESD event. An ESD event typically occurs when the chip is exposed to static electricity, such as when the pins or solder bumps of the chip are touched by an ungrounded person handling the chip, or when the chip slides across another surface on its pins or solder bumps.
For example, an ungrounded person handling a semiconductor chip can place a static electric charge as high as 2000V on the chip. This voltage is more than sufficient to destructively break down the gate oxide of the input/output transistors of the chip.
FIG. 1 shows a schematic diagram that illustrates a prior-art ESD protection circuit 100. As shown in FIG. 1, circuit 100 includes an ESD plus ring 110 and an ESD minus ring 112 that are formed around the periphery of a semiconductor die 114. In addition, circuit 100 includes a power pad 120, a ground pad 122, and a number of input/output (I/O) pads 124.
As further shown in FIG. 1, circuit 100 includes a plurality of upper diodes D1 that are connected to ESD plus ring 110 and the pads 120, 122, and 124 so that each pad is connected to ESD plus ring 110 via a diode D1. In addition, a plurality of lower diodes D2 are connected to ESD minus ring 112 and the pads 120, 122, and 124 so that each pad is connected to ESD minus ring 112 via a diode D2. Circuit 100 also includes four corner clamps 130 that are connected to ESD plus ring 110 and ESD minus ring 112.
In operation, when an ESD event occurs, a first pad, such as pad A, is zapped positively with respect to a second pad, such as pad B. In this situation, a zap current IZAP flows from the first pad through the adjacent diode D1 to ESD plus ring 110, and then on to corner clamps 130.
Corner clamps 130 are voltage controlled switches that each provide a low impedance pathway from ESD positive ring 110 to ESD negative ring 112 when an ESD event is present, and a high impedance pathway between rings 110 and 112 when an ESD event is not present.
When the first pad is zapped, the corner clamps 130 (which are shown open, not closed, in FIG. 1) close and the zap current IZAP flows through clamps 130 to ESD minus ring 112. From ring 112, the zap current IZAP flows through a diode D2 and on to the second pad.
FIG. 2 shows a schematic diagram that illustrates corner clamp 130. As shown in FIG. 2, clamp 130 includes a RC timing circuit 210, an inverter 212, and a switching transistor M1. Timing circuit 210, in turn, includes a resistor R that is connected to ESD plus ring 110, and a capacitor C that is connected to resistor R and ESD minus ring 112.
Inverter 212 includes a PMOS transistor M2 and a NMOS transistor M3. Transistor M2 has a source connected to ESD plus ring 110, a gate connected to resistor R and capacitor C, and a drain. Transistor M3 has a source connected to ESD minus ring 112, a gate connected to resistor R and capacitor C, and a drain connected to the drain of transistor M2. Further, switching transistor M1 has a source connected to ESD minus ring 112, a gate connected to the drains of transistors M2 and M3, and a drain connected to ESD plus ring 110.
In operation, when an ESD event occurs and the zap current IZAP flows onto ESD plus ring 110, the voltage on ESD plus ring 110 spikes up dramatically. The voltage on the gates of transistors M2 and M3 also spikes up but, due to the presence of RC timing circuit 110, the gate voltage lags the voltage on ESD plus ring 110.
As a result, the gate-to-source voltage of transistor M2 falls below the threshold voltage of transistor M2, thereby turning on transistor M2 for as long as the gate voltage lags the voltage on ring 110. When transistor M2 turns on, transistor M2 pulls up the voltage on the gate of transistor M1, thereby turning on transistor M1. When transistor M1 is turned on, clamp 130 provides a low impedance pathway from ESD plus ring 110 to ESD minus ring 112.
Once the packaged integrated circuit has been attached to a circuit board, power has been applied to the integrated circuit, and a steady state condition has been reached, a first voltage is present on both ESD plus ring 110 and the gates of transistors M2 and M3. For example, when pad 120 is a 3.3V power pad, a first voltage of 2.6V is present on ESD plus ring 110 due to the diode drop of adjacent diode D1. In addition, a second voltage is present on ESD minus ring 112. For example, since pad 122 is ground, a second voltage of 0.7V is present on ESD minus ring 112 due to the diode drop of adjacent diode D2.
Since the first voltage is present on the gates of transistors M2 and M3, transistor M2 is turned off and transistor M3 is turned on. When turned on, transistor M3 pulls down the voltage on the gate of transistor M1, thereby turning off transistor M1. When transistor M1 is turned off, clamp 130 provides a high impedance pathway from ESD plus ring 110 to ESD minus ring 112.
One problem with clamp 130 is that clamp 130 falsely triggers when used with a 5V tolerant circuit. A 5V tolerant circuit is a circuit that internally utilizes a voltage less than 5V, such as 3.3V, but receives 5V signals. For example, I/O pad C in FIG. 1 can be driven by an external driver that outputs signals ranging from zero to 5V.
When 5V signals are driven onto a signal pad, such as pad C, the voltage on ESD plus ring 110 spikes up from 2.6V to 4.3V (a diode drop less than 5V). In addition, when a large number of pads are driven to 5V at the same time, such as when the 64 pads of a PCI bus are simultaneously driven high, the voltage on ESD plus ring 110 can spike up to 4.8V.
Due to the timing lag provided by RC timing circuit 210, the spike in voltage, a delta of 1.7V to 2.2V, causes the gate-to-source voltage of transistor M2 to again fall below the threshold voltage, thereby turning on transistor M2. When transistor M2 turns on, transistor M2 pulls up the voltage on the gate of transistor M1, thereby turning on transistor M1.
Since transistor M1 turned on in response to a 5V signal rather than in response to an ESD event, clamp 130 was falsely triggered. Falsely triggering clamp 130 increases power dissipation and significantly loads the external device that is driving the signal pad.
Thus, there is a need for a 5V tolerant corner clamp that does not falsely trigger when a 5V signal is driven onto a signal pad.
The present invention provides a 5V tolerant ESD corner clamp that does not falsely trigger when a 5V signal is driven onto a signal pad. A corner clamp in accordance with the present invention includes a clamp circuit that is connected to an electrostatic discharge (ESD) plus ring and an ESD minus ring.
The clamp circuit has a timing circuit that has a resistive element that is connected to the ESD plus ring and a first node. The clamp circuit also has a pre-driver circuit that is connected to the timing circuit. The pre-driver circuit includes a first transistor that is connected to the ESD plus ring. The first transistor turns on when a difference between a voltage on the ESD plus ring and a voltage on the first node exceeds a predetermined amount. The clamp circuit further has a switching circuit that is connected to the pre-driver circuit, the ESD plus ring, and the ESD minus ring.
The corner clamp of the present invention also includes a keep off circuit that is connected to the clamp circuit, the ESD plus ring, and the ESD minus ring. The keep off circuit has a control circuit that is connected to the first node. The control circuit has an output. In addition, the keep off circuit includes a keep off transistor that is connected to the ESD plus ring, the first node, and the output of the control circuit. The keep off transistor provides a current path from the ESD plus ring to the first node when turned on.
A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description and accompanying drawings that set forth an illustrative embodiment in which the principles of the invention are utilized.